Sunil Sharma
Pre-silicon bug hunter: SystemVerilog, UVM and IP/SoC verification
I'm a design verification engineer who helps semiconductor teams get unstable testbenches under control. I fix SystemVerilog and UVM environment problems, close functional coverage gaps, and shorten regression cycles so a team can trust its results.
My project work has covered MIPI M-PHY and UniPro, CSI-3, RS-232/RS-485, SPI and APB/AHB buses for clients including Intel, Renesas, Toshiba, Infineon etc. I'm based in India.
What I've delivered
10% more coverageClosed MTX and MRX coverage gaps on an M-PHY 3.0 verification project.
About 20% faster regressionsGraded the coverage model on a CSI-3 project to cut turnaround time.
About 30% less debug timeBuilt UVM_ALIGNER, a Perl tool that automates UVM VIP formatting to coding guidelines (alpha).
What I work with
- Verification
- SystemVerilog, UVM, SVA assertions, constrained-random verification, functional coverage
- Protocols
- MIPI M-PHY 3.0, UniPro 1.6, CSI-3 (CAL layer), RS-232/RS-485, SPI, UART, AHB, APB
- Tools
- VCS, QuestaSim, DVE, Synopsys VIP
- Debug and scripting
- Waveform and scoreboard debug, coverage analysis, Perl, Shell, Unix